Fault tolerant arithmetic unit using duplication and residue codes
Integration, the VLSI Journal
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
Optical Fault Induction Attacks
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
On a New Way to Read Data from Memory
SISW '02 Proceedings of the First International IEEE Security in Storage Workshop
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast Digital TRNG Based on Metastable Ring Oscillator
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
A Practical Fault Attack on Square and Multiply
FDTC '08 Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-linear Error Detection for Finite State Machines
Information Security Applications
Low Voltage Fault Attacks on the RSA Cryptosystem
FDTC '09 Proceedings of the 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography
Fault attacks for CRT based RSA: new attacks, new results and new countermeasures
WISTP'07 Proceedings of the 1st IFIP TC6 /WG8.8 /WG11.2 international conference on Information security theory and practices: smart cards, mobile and ubiquitous computing systems
FDTC '10 Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography
Multi Fault Laser Attacks on Protected CRT-RSA
FDTC '10 Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography
Robust FSMs for cryptographic devices resilient to strong fault injection attacks
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA
Journal of Cryptology - Special Issue on Hardware and Security
Case study of a fault attack on asynchronous DES crypto-processors
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
A comparative cost/security analysis of fault attack countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Non-linear residue codes for robust public-key arithmetic
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Design of reliable and secure multipliers by multilinear arithmetic codes
ICICS'09 Proceedings of the 11th international conference on Information and Communications Security
Cyclic and multiresidue codes for arithmetic operations
IEEE Transactions on Information Theory
| Hi-index | 0.00 |
Public-key cryptographic devices are vulnerable to fault-injection attacks. As countermeasures, a number of secure architectures based on linear and nonlinear error detecting codes were proposed. Linear codes provide protection only against primitive adversaries with limited attack capabilities. On the other hand nonlinear codes provide protection against strong adversaries, but at the price of high area overhead (200%-400%). In this paper we propose a novel error detection technique based on the random selection of linear arithmetic codes and explore the use of this technique for the protection of the multiplier, which is a basic block in many public-key cryptographic devices. The error detection technique does not imply any limitations on the types of errors at the output of the device, e.g., the multiplicity of the error does not have to be small. Under mild assumptions the proposed construction achieves near nonlinear code error detection performance at a lower cost (at most 50% area overhead for the protection of multipliers) due to the fact that no nonlinear operations are needed for the encoder and decoder.