On the generation of small dictionaries for fault location
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Bridge Defect Diagnosis with Physical Information
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
DERRIC: A Tool for Unified Logic Diagnosis
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Resistive Bridging Faults DFT with Adaptive Power Management Awareness
ATS '07 Proceedings of the 16th Asian Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Simulating Resistive-Bridging and Stuck-At Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridging Fault Test Method With Adaptive Power Management Awareness
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing for SoCs with advanced static and dynamic power-management capabilities
Proceedings of the Conference on Design, Automation and Test in Europe
Secure multipliers resilient to strong fault-injection attacks using multilinear arithmetic codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.