Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Detection of Defects Using Fault Model Oriented Test Sequences
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Bridging fault coverage improvement by power supply control
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Automatic Test Pattern Generation for Resistive Bridging Faults
Journal of Electronic Testing: Theory and Applications
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-for-testability for path delay faults in large combinational circuits using test points
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulating Resistive-Bridging and Stuck-At Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bridging Fault Test Method With Adaptive Power Management Awareness
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On testing timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.03 |
The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS and ITC benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves single Vdd test, without affecting the fault coverage of the original test. In addition, the proposed technique performs better in terms of timing, area, and power than the recently proposed test point insertion technique. This is the first reported work that achieves single Vdd test for resistive bridge defects, without compromising fault coverage in multi-Vdd designs.