Crosstalk fault modeling in defective pair of interconnects
Integration, the VLSI Journal
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Process variation-aware test for resistive bridges
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel X-fault simulation with critical path tracing technique
Proceedings of the Conference on Design, Automation and Test in Europe
Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling of crosstalk fault in defective interconnects
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests.