Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
Adaptive Debug and Diagnosis Without Fault Dictionaries
Journal of Electronic Testing: Theory and Applications
Diagnosis of multiple-voltage design with bridge defect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Employing test suites for verilog fault localization
CAEPIA'09 Proceedings of the Current topics in artificial intelligence, and 13th conference on Spanish association for artificial intelligence
On undetectable faults and fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.