A theory of diagnosis from first principles
Artificial Intelligence
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterizing diagnoses and systems
Artificial Intelligence
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Debugging Hardware Designs Using a Value-Based Model
Applied Intelligence
Modeling the Unmodelable: Algorithmic Fault Diagnosis
IEEE Design & Test
Automated Source-Level Error Localization in Hardware Designs
IEEE Design & Test
Debugging VHDL designs using temporal process instances
IEA/AIE'2003 Proceedings of the 16th international conference on Developments in applied artificial intelligence
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
DERRIC: A Tool for Unified Logic Diagnosis
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Test Patterns for Verilog Design Error Localization
TAIC-PART '09 Proceedings of the 2009 Testing: Academic and Industrial Conference - Practice and Research Techniques
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
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This article briefly states the idea behind model-based diagnosis and its application to localizing faults in Verilog programs. Specifically this article outlines how to employ a test suite to further reduce the number of fault candidates. For this purpose, we propose the filtering approach and relate it to the concept of Ackermann constraints. Notably, our empirical results demonstrate that our novel technique considerably increases the diagnosis resolution even under presence of only a couple of test cases.