SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Aspect: detecting bugs with abstract dependences
ACM Transactions on Software Engineering and Methodology (TOSEM)
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
A VHDL Fault Diagnosis Tool Using Functional Fault Models
IEEE Design & Test
Program Slicing of Hardware Description Languages
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
HORNSAT, Model Checking, Verification and games (Extended Abstract)
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Error traces in model-based debugging of hardware description languages
Proceedings of the sixth international symposium on Automated analysis-driven debugging
Improving Robustness of Mobile Robots Using Model-based Reasoning
Journal of Intelligent and Robotic Systems
Automated Fault Localization for C Programs
Electronic Notes in Theoretical Computer Science (ENTCS)
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Does testing help to reduce the number of potentially faulty statements in debugging?
TAIC PART'10 Proceedings of the 5th international academic and industrial conference on Testing - practice and research techniques
Employing test suites for verilog fault localization
CAEPIA'09 Proceedings of the Current topics in artificial intelligence, and 13th conference on Spanish association for artificial intelligence
CAEPIA'09 Proceedings of the Current topics in artificial intelligence, and 13th conference on Spanish association for artificial intelligence
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Journal of Computer and System Sciences
Towards lightweight fault localization in procedural programs
IEA/AIE'06 Proceedings of the 19th international conference on Advances in Applied Artificial Intelligence: industrial, Engineering and Other Applications of Applied Intelligent Systems
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Recent achievements in formal verification techniques allow for fault detection even in large real-world designs. Tool support for localizing the faulty statements is critical, because it reduces development time and overall project costs. Automated source-level debugging and a new and novel debugging model allow for source-level debugging of large VHDL designs at the granularity of statements and expressions. This technique is fully automated and does not require that an engineer be familiar with formal verification techniques.