A theory of diagnosis from first principles
Artificial Intelligence
Artificial Intelligence
A correction to the algorithm in Reiter's theory of diagnosis
Artificial Intelligence
Aspect: detecting bugs with abstract dependences
ACM Transactions on Software Engineering and Methodology (TOSEM)
Model-based diagnosis of hardware designs
Artificial Intelligence
New directions in debugging hardware designs
IEA/AIE '99 Proceedings of the 12th international conference on Industrial and engineering applications of artificial intelligence and expert systems: multiple approaches to intelligent systems
Programmers use slices when debugging
Communications of the ACM
On the relationship between model-based debugging and program slicing
Artificial Intelligence
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Debugging Hardware Designs Using a Value-Based Model
Applied Intelligence
Dependency-Directed Localization of Software Bugs
Dependency-Directed Localization of Software Bugs
Symbolic diagnosis and its formalisation
The Knowledge Engineering Review
Diagnosing tree-decomposable circuits
IJCAI'95 Proceedings of the 14th international joint conference on Artificial intelligence - Volume 2
Temporal model-based diagnostics generation for HVAC control systems
ICMT'10 Proceedings of the Third international conference on Theory and practice of model transformations
Employing test suites for verilog fault localization
CAEPIA'09 Proceedings of the Current topics in artificial intelligence, and 13th conference on Spanish association for artificial intelligence
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In this paper we outline the usage of model-based diagnosis for fault localization in VHDL-RTL designs. In contrast to previous research, our approach makes use of temporal aspects of a VHDL program. The facts that the conversion of the VHDL program to a logical representation can be done automatically, and that a standard model-based diagnosis engine can be used, make the approach easy to implement and use. In the first part of the paper, we show how a model can be used to compute diagnosis for a VHDL program. In the second part, we introduce a new logical model that allows the diagnosis engine to deal with temporal information directly by unfolding the circuit with respect to time, thereby employing temporal instances of VHDL processes.