On the generation of small dictionaries for fault location
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
On adaptive diagnostic test generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Diagnosis of realistic bridging faults with single stuck-at information
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Signature Analysis for IC Diagnosis and Failure Analysis
Proceedings of the IEEE International Test Conference
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Probabilistic mixed-model fault diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
Full fault dictionary storage based on labeled tree encoding
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Fault Distinguishing Pattern Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Effective Diagnosis Method to Support Yield Improvement
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Stuck-Open Fault Diagnosis with Stuck-At Model
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
From Embedded Test to Embedded Diagnosis
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Some Common Aspects of Design Validation,Debug and Diagnosis
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
Test Consideration for Nanometer-Scale CMOS Circuits
IEEE Design & Test
Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structural Test and Diagnosis for Graceful Degradation of NoC Switches
Journal of Electronic Testing: Theory and Applications
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Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for `Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.