Yield Analysis of Logic Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Understanding Yield Losses in Logic Circuits
IEEE Design & Test
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Yield Enhancement Methodology for CMOS Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Adaptive Debug and Diagnosis Without Fault Dictionaries
Journal of Electronic Testing: Theory and Applications
DREAMS: DFM rule EvAluation using manufactured silicon
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
The ability to achieve and maintain high yield levels depends on the capability of detecting, analyzing and correcting repetitive failure mechanisms. In this paper, a statistical fault diagnosis method based on using only the first or the first few failing test vectors is presented. The new approach is analyzing the failing vectors from an entire lot and produces a finite list of suspect locations, which are then subjected to further statistical and physical analysis. The results of the performed case studies show the usefulness of this method when applied in a production environment. We were able to detect repetitive failure mechanisms and accurately correlate electrical fail locations to in-line inspection data and thus greatly improve the accuracy of the determined kill ratio.