Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
IEEE Design & Test
Diagnosis of Scan Chain Failures
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A highly testable and diagnosable fabrication process test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Effective Diagnosis Method to Support Yield Improvement
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Understanding Yield Losses in Logic Circuits
IEEE Design & Test
Product on-chip process compensation for low power and yield enhancement
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In order to maximize the yield of random logic in today's advanced Deep Sub-Micron CMOS technologies we have developed a complete yield enhancement methodology for Cmos standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper will explain the methodology and demonstrate the results and benefits of this work through illustrated examples.