Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Yield Enhancement Methodology for CMOS Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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We present the concept and prototype of theLogic Test Vehicle (LTV), a novel tool forramp-up, qualification and monitoring ofsemiconductor fabrication processes. The LTVovercomes some of the known shortcomings ofSRAM test vehicle used today for thesepurposes. It employs test circuitry which ismore complex and more representative of thecomplexities found on real products yet retainstestability and diagnosability, the two mostimportant attributes required of test vehicles.