Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A highly testable and diagnosable fabrication process test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On improving genetic optimization based test generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BOARD LEVEL AUTOMATED FAULT INJECTION FOR FAULT COVERAGE AND DIAGNOSTIC EFFICIENCY
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test chip experimental results on high-level structural test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
System-level impact of chip-level failure mechanisms and screens
Proceedings of the International Conference on Computer-Aided Design
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