Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On the Compaction of Test Sets Produced by Genetic Optimization
ATS '97 Proceedings of the 6th Asian Test Symposium
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments
Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments
| Hi-index | 14.98 |
Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In this work, we propose a representation of test patterns for genetic optimization based test generation, where subsets of inputs are considered as indivisible entities. Using this representation, crossover between two test patterns $t_1$ and $t_2$ copies all the values of each subset either from $t_1$ or from $t_2$. By keeping input subsets undivided, activation and propagation capabilities of $t_1$ and $t_2$ are expected to be captured and carried over to the new test patterns. Experimental results presented show that the proposed scheme results in complete stuck-at test sets and $n$-detection test sets for combinational circuits, even in cases where other procedures report incomplete fault coverages.