Failure Diagnosis of Structured VLSI
IEEE Design & Test
Shmoo Plotting: The Black Art of IC Testing
IEEE Design & Test
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Effective Diagnosis Method to Support Yield Improvement
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Yield Enhancement Methodology for CMOS Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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Yield improvement requires understanding failures and identifying potential sources of yield loss. This article focuses on diagnosing random logic circuits and classifying faults. The authors introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.