Failure Diagnosis of Structured VLSI
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Automated Diagnosis in Testing and Failure Analysis
IEEE Design & Test
Inductive Contamination Analysis (ICA) with SRAM Application
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Failure Analysis for Full-Scan Circuits
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Diagnostic techniques for the UltraSPARC microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On applying non-classical defect models to automated diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Improvement of SRAM-based failure analysis using calibrated Iddq testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Expediting Ramp-to-Volume Production
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
IEEE Design & Test
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic Mapping on a Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
Journal of Electronic Testing: Theory and Applications
Yield Analysis of Logic Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Understanding Yield Losses in Logic Circuits
IEEE Design & Test
Design/process learning from electrical test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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Traditional yield enhancement efforts have long relied onmemory bitmapping techniques. With the industrymarching toward system-on-a-chip technology, theimportance of logic products has increased exponentially.This necessitates the development of innovativetechniques to perform logic yield enhancement. In thispaper, the authors present a novel technique that can beused to perform logic yield enhancement. The paperconcentrates on logic bitmapping at Texas Instruments.Results obtained from a few production samples of agraphics processor are also presented.