On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up

  • Authors:
  • Camelia Hora;Rene Segers;Stefan Eichenberger;Maurice Lousberg

  • Affiliations:
  • Eindhoven University of Technology, P.O. Box 513, 5600MD Eindhoven. cami@ics.ele.tue.nl;Philips Semiconductors, P.O. Box 218, 5600MB Eindhoven. Rene.segers@philips.com;Philips Semiconductors, Gerstweg 2, 6534AE Nijmegen. Stefan.eichenberger@philips.com;Philips Research Labs, Prof. Holstlaan 4, 5656AA Eindhoven. Maurice.lousberg@philips.com

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2003

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Abstract

This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects ...