Mapping and Repairing Embedded-Memory Defects
IEEE Design & Test
Automated Diagnosis in Testing and Failure Analysis
IEEE Design & Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic techniques for the UltraSPARC microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On applying non-classical defect models to automated diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Improving debug techniques for logic failures is aconstant imperative. This paper describes the resultsof implementing a logic mapping methodology thatintegrates in-line manufacturing defect data andscan-based diagnosis for a complex microprocessor.The correlation between the physical failure analysisresults and defect inspection data is presented andanalyzed. Methods to improve the percentage of'hits' are explored, supported by a detailed accountof challenges and obstacles encountered during theexperiment. Finally, the paper also briefly highlightsthe amount of time that can be saved in processdebug through the usage of logic mapping.