Automated Diagnosis in Testing and Failure Analysis
IEEE Design & Test
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic techniques for the UltraSPARC microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
THE PATH to ONE - PICOSECOND ACCURACY
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DFT Advances in Motorola's Next-Generation 74xx PowerPC" Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Getting Better Coverage from the Tests We Have
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic Mapping on a Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
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A description of test coverage on the UltraSPARCfamily of devices is presented. Techniques developedwith the intent to reduce "functional only" failuresare discussed along with the resulting impact to themanufacturing process.