CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 0.00 |
IDDQ testing has been introduced to CMOS production lines for achieving higher quality and reliability. In addition, electrical stress applying method called High Voltage Stress (HVS) method was proposed for reliable rejection of weak insulation (such as gate oxide and interlayer separators). The capability of IDDQ testing and HVS method for elimination of burn-in process, an effective method to guarantee reliability but expensive, was investigated. The reduction of burn-in failure rate of 1.0um product by introducing IDDQ testing prior to burn-in indicated that burn-in elimination was possible. Based on this result, burn-in elimination was accomplished for 0.5um products followed by HVS method adoption. Failure analysis on IDDQ rejects of 0.5um products have clarified IDDQ+HVS as alternative cost effective technology of conventional burn-in. Further investigation revealed that even IDDQ+HVS was not effective enough for screening devices made from badly contaminated wafers.