Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Efficient testing of clock regenerator circuits in scan designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Next-Generation PowerPCTM Microprocessor Test Strategy Improvements
Proceedings of the IEEE International Test Conference
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Integrated Diagnostics for Embedded Memory Built-in Self Test on PowerPCTM Devices
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Design-For-Test Methodology for Motorola PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
MODELING AND TESTING THE GEKKO MICROPROCESSOR, AN IBM POWERPC DERIVATIVE FOR NINTENDO
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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This paper shares techniques used to overcome DFTchallenges on Motorola's Next-Generation 74xx PowerPC(tm) microprocessor - a 700+ MHz microprocessorwith an on-chip, 256K byte second-level cache.