Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates

Using Partial Isolation Rings to Test Core-Based Designs

IEEE Design & Test

Static logic implication with application to redundancy identification

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Testing Embedded Cores Using Partial Isolation Rings

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Using ATPG for clock rules checking in complex scan designs

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

DFT Advances in Motorola's Next-Generation 74xx PowerPC" Microprocessor

ITC '00 Proceedings of the 2000 IEEE International Test Conference

OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Tailoring ATPG for Embedded Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A Novel Functional Test Generation Method for Processors using Commercial ATPG

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Modeling Custom Digital Circuits for Test

Journal of Electronic Testing: Theory and Applications