Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Behavioral-Test Generation using Mixed-Integer Non-linear Programming
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A Novel Hierarchical Test Generation Method for Processors
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
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As the sizes of general and special purpose processorsincrease rapidly, generating high quality manufacturingtests for them is becoming a serious problem in industry.This paper describes a novel method for hierarchicalfunctional test generation for processors which targetsone embedded module at a time and uses commercialATPG tools to derive tests for faults within the module.Applying the technique to benchmark processor designs,we were able to obtain test efficiencies for the embeddedmodules of the processors which were extremely close towhat the commercial ATPG could do with completeaccess to the module. The hierarchical approach usedproduced this result, using the same commercial tool,but required a CPU time several orders of magnitudeless than when using a conventional, flat view of thecircuit.