Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Some Prospects for Efficient Fixed Parameter Algorithms
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Logic Mapping on a Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Memory Built-In Self-Repair using redundant words
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Online diagnosis of hard faults in microprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Diagnosis and repair method of SoC memory
WSEAS Transactions on Circuits and Systems
Optimal embedded repairing of SOC memory
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
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Yield is perhaps the single most important measure of manufacturing efficiency for large integrated circuits. To reduce product time-to-volume and accelerate continuous yield improvement, we have integrated memory test, defect mapping, and repair into the UltraSPARC microprocessor manufacturing flow.We use the UltraSPARC memory test port, together with standard memory test equipment and integrated software to detect, locate, and repair defects in the larger memory arrays. Pattern-recognized memory defect maps are collected for every chip manufactured, accelerating the understanding of defects and their causes. As part of the manufacturing process, we also program a unique identity into each chip that can be read electrically. In this article, we present the memory defect-mapping system that has been established and our use of that system to accelerate yield learning.