Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
Mapping and Repairing Embedded-Memory Defects
IEEE Design & Test
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Repair of Memory Arrays by Cutting
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
An Efficient Perfect Algorithm for Memory Repair Problems
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Defect repair has become a necessary process to enhance the overall yield for memories since manufacturing a natural good memory is difficult in current memory technologies. This paper presents an yield-estimation scheme, which utilizes an induction-based approach to calculate the probability that all defects in a memory can be successfully repaired by a two-dimensional redundancy design. Unlike previous works, which rely on a time-consuming simulation to estimate the expected yield, our yield-estimation scheme only requires scalable mathematical computation and can achieve a high accuracy with limited time and space complexity. Also, the proposed estimation scheme can consider the impact of single defects, column defects, and row defects simultaneously. With the help of the proposed yield-estimation scheme, we can effectively identify the most profitable redundancy configuration for large memory designs within few seconds while it may take several hours or even days by using conventional simulation approach.