A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
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We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature 驴 it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.