Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
IEEE Design & Test
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs
Proceedings of the IEEE International Test Conference 2001
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
An Approach for Evaluation of Redunancy Analysis Algorithms
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
Fault simulation and test algorithm generation for random access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
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Embedded memories are among the most widely used cores in current SoC designs. Memory cores usually dominate the area and yield of the system chip, requiring repair methodologies to make a profitable product. To increase the efficiency of redundancy repair, and thus final yield, the authors propose Raisin (Redundancy Analysis Algorithm Simulation). The Raisin tool calculates the repair rate and yield (after repair) of the given redundancy analysis (RA) algorithm and the associated memory configuration and redundancy structure. With Raisin, users can easily assess and plan redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential to built-in self-repair of embedded memories. To make the verification of the BISR design easier, Raisin also generates its testbench. Another important feature is that given a RAM test algorithm, Raisin simulates the real sequence of the faults detected, improving the accuracy of the analysis results. Experimental results show that Raisin can improve repair rates in redundancy structures by as much as 10% without increasing area overhead. Raisin has been used in industry cases, including embedded SRAM and flash memory circuits.