Embedding infrastructure IP for SOC yield improvement
Proceedings of the 39th annual Design Automation Conference
Guest Editor's Introduction: What is Infrastructure IP?
IEEE Design & Test
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Address and Data Scrambling: Causes and Impact on Memory Tests
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Approach for Evaluation of Redunancy Analysis Algorithms
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis and repair method of SoC memory
WSEAS Transactions on Circuits and Systems
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Optimal embedded repairing of SOC memory
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Modified essential spare pivoting algorithm for embedded memories with global block-based redundancy
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Editor's note:Today's complex SoCs need sophisticated infrastructure IP, not only to test and diagnose embedded memories but also to repair them and improve fabrication yield. The authors' solution integrates memory IP with test and repair IP in a composite infrastructure IP that ensures manufacturing and field repair efficiency and optimizes SoC yield.ýPaolo Prinetto, Politecnico di Torino