Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
| Hi-index | 0.00 |
Yield improvement is an essential issue for modern high-volume manufacturing CMOS processes. Process yield is particularly low for area-critical designs, such as embedded memories. The use of redundancy structures which replace faulty memory locations with good ones, has a direct impact on the final chip yield. This paper describes an experimental methodology employed to evaluate the yield gain associated with different redundancy approaches and shows how this method can be applied to determine the optimal redundancyconfiguration which maximizes the number of good dies per wafer, depending on the embedded memory requirements of a specific product.