Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: An approach for design and evaluation of redundancy analysis algorithms based on vectors of preferences is proposed for memory devices with spare elements. Experiments on the application of the new algorithms for Self-Test and Repair (STAR) type SRAM memories have shown the efficiency of the proposed approach.