Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March-based RAM diagnosis algorithms for stuck-at and coupling faults
Proceedings of the IEEE International Test Conference 2001
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Address and Data Scrambling: Causes and Impact on Memory Tests
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A March-Based Fault Location Algorithm for Static Random Access Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Approach for Evaluation of Redunancy Analysis Algorithms
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Thorough testing of any multiport memory with linear tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level SRAM Yield Enhancement
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Diagnosis and repair method of SoC memory
WSEAS Transactions on Circuits and Systems
Optimal embedded repairing of SOC memory
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A low power JPEG2000 encoder with iterative and fault tolerant error concealment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
An alternative organization of defect map for defect-resilient embedded on-chip memories
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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Today, embedded memories are the most important contributor to SoC yield. To maximize embedded-memory yield, advanced test and repair solutions must be an integral part of the memory block. This article analyzes factors that affect memory yield and presents advanced techniques for maximizing their positive impact.