An alternative organization of defect map for defect-resilient embedded on-chip memories

Authors:
Kang Yi;Shih-Yang Cheng;Young-Hwan Park;Fadi Kurdahi;Ahmed Eltawil
Affiliations:
School of Computer Sceince and Electronic Engineering, Handong Global University, Pohang, Korea;Department of EECS, University of California, Irvine, CA;Department of EECS, University of California, Irvine, CA;Department of EECS, University of California, Irvine, CA;Department of EECS, University of California, Irvine, CA
Venue:
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2007

Citing 5
Cited 0

SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure

IEEE Design & Test
A process-tolerant cache architecture for improved yield in nanoscale technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-Level SRAM Yield Enhancement

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design and analysis of low power image filters toward defect-resilient embedded memories for multimedia socs

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
H.264/AVC baseline profile decoder complexity analysis

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose the low power and low area defect map organization for the defect-resilient embedded memory system for multimedia SOCs. Existing approach to build defect map of embedded memories is based on the CAM (Content Addressable Memory) organization. But, it consumes too much power and relatively large chip area. It may be serious problem in the near future for very deep submicron technologies. Therefore, we propose the SRAM-based defect map organization to reduce both the power consumption and chip area. We also develop new defect map access algorithm to minimize the number of defect map access operations to save power. Our estimation results show the new scheme based on SRAM defect map organization consumes only 1/4 times of power at BER=1.0% compared with the power overhead by the existing approach.