Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
IEEE Design & Test
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross Layer Error Exploitation for Aggressive Voltage Scaling
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A scalable embedded JPEG2000 architecture
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Motion JPEG2000 for high quality video systems
IEEE Transactions on Consumer Electronics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Salt-and-pepper noise removal by median-type noise detectors and detail-preserving regularization
IEEE Transactions on Image Processing
Deblurring of Color Images Corrupted by Impulsive Noise
IEEE Transactions on Image Processing
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for compensating memory errors in JPEG2000
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hi-index | 0.00 |
This paper presents a novel approach to reduce power in multimedia devices. Specifically, we focus on JPEG2000 as a case study. This paper indicates that by utilizing the in-built error resiliency of multimedia content, and the disjoint nature of the encoding and decoding processes, ultra low power architectures that are hardware fault tolerant can be conceived. These architectures utilize aggressive voltage scaling to conserve power at the encoder side while incurring extra processing requirements at the decoder to blindly detect and correct for encoder hardware induced errors. Simulations indicate a reduction of up to 35% in encoder power depending on the choice of technology for a 65-nm CMOS process.