A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
A scalable and programmable architecture for 2-D DWT decoding
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance JPEG2000 architecture
IEEE Transactions on Circuits and Systems for Video Technology
Formal performance evaluation of AMBA-based system-on-chip designs
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
A low power JPEG2000 encoder with iterative and fault tolerant error concealment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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It takes more than a good tool to shorten the time-to-market window: the scalability of a design also plays an important role in rapid prototyping if it needs to satisfy various demands. The design of JPEG2000 belongs to such cases. As the latest compression standard for still images, JPEG2000 is well tuned for diverse applications, raising different throughput requirements on its composed blocks. In this paper, a scalable embedded JPEG2000 encoder architecture is presented and prototyped onto Xilinx FPGA. The system level design presents dynamic profiling outcomes, proving the necessity of the design for scalability.