A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

Authors:
Chien-Yu Chen;Zhong-Lan Yang;Tu-Chih Wang;Liang-Gee Chen
Affiliations:
Department of Electrical Engineering, National Taiwan University, 1, Roosevelt Rd. Sec. 4, Taipei, Taiwan, R.O.C. 10617;Department of Electrical Engineering, National Taiwan University, 1, Roosevelt Rd. Sec. 4, Taipei, Taiwan, R.O.C. 10617;Department of Electrical Engineering, National Taiwan University, 1, Roosevelt Rd. Sec. 4, Taipei, Taiwan, R.O.C. 10617;Department of Electrical Engineering, National Taiwan University, 1, Roosevelt Rd. Sec. 4, Taipei, Taiwan, R.O.C. 10617
Venue:
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Year:
2001

Citing 5
Cited 6

VLSI implementation of discrete wavelet transform

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform

Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
A Very Efficient Storage Structure for DWT and IDWT Filters

Journal of VLSI Signal Processing Systems
Discrete wavelet transform: data dependence analysis and synthesisof distributed memory and control array architectures

IEEE Transactions on Signal Processing
Efficient realizations of the discrete and continuous wavelettransforms: from single chip implementations to mappings on SIMD arraycomputers

IEEE Transactions on Signal Processing

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

Journal of VLSI Signal Processing Systems
Handling finite length signals borders in two-channel multirate filter banks for perfect reconstruction

Signal Processing
Optimized memory requirements for wavelet-based scalable multimedia codecs

Journal of Embedded Computing - Low-power Embedded Systems
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A scalable embedded JPEG2000 architecture

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Algorithms and architectures for 2D discrete wavelet transform

The Journal of Supercomputing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 &mgr;m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 &mgr;m × 2500 &mgr;m. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.