A Very Efficient Storage Structure for DWT and IDWT Filters

  • Authors:
  • Robert M. Owens;Mohan Vishwanath

  • Affiliations:
  • Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802;Vidam Communications Inc., 2, N. First Street, San Jose, CA

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 1998

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Abstract

In this paper, we present an area-efficient storage and routingstructure to be used as part of either a DWT or an IDWT filter.Such efficient structures are necessary for the single chipimplementation of multidimensional DWT and IDWT filters forprocessing images and video. While the storage structuresdescribed in previously published architectures were adequatefor the 1D DWT/IDWT filter, they do not scale well to amultidimensional implementation. The storage structure designand implementation described in this paper utilizes acombination of well-known efficient RAM cells with simple controlto achieve compact size and scalability. When compared to otheralternatives, the structure uses less power.In this paper, we examine the problem of constructing, on asingle chip, filters for both the multidimensional DiscreteWavelet Transform (DWT) and the multidimensional InverseDiscrete Wavelet Transform (IDWT). We will use the followingexample to illustrate where the difficulty lies in constructingsuch a chip. Consider a filter that executes transforms on 2Dimages at the rate of 30 images per second. Furthermore, thesize N × N of the images is 1024× 1024, the length L ofthe filter is 8, the number of octaves O to be generatedis 4, and the arithmetic precision P is 24. Inimage compression, such a filter would be a good candidate forthe replacement of the filters presently used to perform theblock Discrete Cosine Transform (DCT).