Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design Challenges of Technology Scaling
IEEE Micro
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Implications of technology scaling on leakage reduction techniques
Proceedings of the 40th annual Design Automation Conference
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Process variation aware SRAM/cache for aggressive voltage-frequency scaling
Proceedings of the Conference on Design, Automation and Test in Europe
A low power JPEG2000 encoder with iterative and fault tolerant error concealment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present the "Variation Trained Drowsy Cache" (VTD-Cache) architecture. VTD-Cache allows for a significant reduction in power consumption while addressing reliability issues raised by memory cell process variability. By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and the likelihood of access to that cache location. After a short training period, the proposed architecture will micro-tune the cache, allowing significant power reduction with negligible increase in the number of misses. In addition, the proposed architecture actively monitors the access pattern and reconfigures the supply voltage setting to adapt to the execution pattern of the program. The novel and modular architecture of the VTD-Cache and its associated controller makes it easy to be implemented in memory compilers with a small area and power overhead. In a case study, the SimpleScalar simulation of the proposed 32 kB cache architecture reports over 57% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead of less than 4% and an execution time penalty smaller than 1%.