Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Proceedings of the 40th annual Design Automation Conference
Ultralow-power SRAM technology
IBM Journal of Research and Development
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 43rd annual Design Automation Conference
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Worst-case design and margin for embedded SRAM
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A methodology for statistical estimation of read access yield in SRAMs
Proceedings of the 45th annual Design Automation Conference
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Tolerating process variations in large, set-associative caches: The buddy cache
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
The salvage cache: a fault-tolerant cache architecture for next-generation memory technologies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation aware SRAM/cache for aggressive voltage-frequency scaling
Proceedings of the Conference on Design, Automation and Test in Europe
Low-power multimedia system design by aggressive voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of RDF and RTS on the performance of SRAM cells
Journal of Computational Electronics
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Exponent monte carlo for quick statistical circuit simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon
Proceedings of the 49th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We have analyzed and modeled the failure probabilities of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip based on the cell failure probability is proposed. The developed method is used in an early stage of a design cycle to minimize memory failure probability by statistically sizing of SRAM cell.