Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Worst-case design and margin for embedded SRAM
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Yield-driven near-threshold SRAM design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient method for statistical circuit simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 13th international symposium on Low power electronics and design
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
SRAM dynamic stability: theory, variability and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A taylor series methodology for analyzing the effects of process variation on circuit operation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Statistical static timing analysis: A survey
Integration, the VLSI Journal
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Yield-driven iterative robust circuit optimization algorithm
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design
Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability
Integration, the VLSI Journal
Self-repairing SRAM using on-chip detection and compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
A holistic approach for statistical SRAM analysis
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical SRAM analysis for yield enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
Correlation controlled sampling for efficient variability analysis of analog circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A discussion on SRAM circuit design trend in deeper nanometer-scale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph partition based path selection for testing of small delay defects
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Two fast methods for estimating the minimum standby supply voltage for large SRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yield-driven near-threshold SRAM design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM write-ability improvement with transient negative bit-line voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The impact of statistical leakage models on design yield estimation
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A novel column-decoupled 8T cell for low-power differential and domino-based SRAM design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient SRAM failure rate prediction via Gibbs sampling
Proceedings of the 48th Design Automation Conference
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
Proceedings of the 48th Design Automation Conference
Exponent monte carlo for quick statistical circuit simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Universal statistical cure for predicting memory loss
Proceedings of the International Conference on Computer-Aided Design
Accelerated statistical simulation via on-demand Hermite spline interpolations
Proceedings of the International Conference on Computer-Aided Design
Maximum-information storage system: concept, implementation and application
Proceedings of the International Conference on Computer-Aided Design
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis
Proceedings of the International Conference on Computer-Aided Design
A fast estimation of SRAM failure rate using probability collectives
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Yield estimation via multi-cones
Proceedings of the 49th Annual Design Automation Conference
Classifying circuit performance using active-learning guided support vector machines
Proceedings of the International Conference on Computer-Aided Design
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN
Proceedings of the Conference on Design, Automation and Test in Europe
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Proceedings of the 50th Annual Design Automation Conference
Cross entropy minimization for efficient estimation of SRAM failure rate
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Advances in variation-aware modeling, verification, and testing of analog ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we propose a novel methodology for statistical SRAM design and analysis. It relies on an efficient form of importance sampling, mixture importance sampling. The method is comprehensive, computationally efficient and the results are in excellent agreement with those obtained via standard Monte Carlo techniques. All this comes at significant gains in speed and accuracy, with speedup of more than 100X compared to regular Monte Carlo. To the best of our knowledge, this is the first time such a methodology is applied to the analysis of SRAM designs.