Self-repairing SRAM using on-chip detection and compensation

Authors:
Niladri Narayan Mojumder;Saibal Mukhopadhyay;Jae-Joon Kim;Ching-Te Chuang;Kaushik Roy
Affiliations:
Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA and High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY;High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY;Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan and High Performance Circuit Design Group, IBM T. J. Watson Research Center, Yorktown Heights, NY;Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement.