Mitigation of intra-array SRAM variability using adaptive voltage architecture
Proceedings of the 2009 International Conference on Computer-Aided Design
Self-repairing SRAM using on-chip detection and compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures in SRAM are due to local random intradie variations, the parametric failures increase at extreme interdie corners. Next, we show that proper BB can reduce different types of parametric failures. Finally, we show that adaptive application of BB to different dies, based on their interdie corners, reduces the total number of parametric failures in those dies. This helps to repair the faulty dies at different interdie corners, thereby improving SRAM yield. We show that postsilicon-tuning using BB can result in significant yield enhancement for SRAM (8%-25% in predictive 70-nm technology).