A discussion on SRAM circuit design trend in deeper nanometer-scale technologies

Authors:
Hiroyuki Yamauchi
Affiliations:
Fukuoka Institute of Technology, Fukuoka, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 5
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Abstract

This paper compares area scaling capabilities of many kinds of SRAM margin-assist solutions for VT variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporation of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever-increasing VT random variation (σVT), resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different σVT-increasing scenarios of being pessimistic and optimistic are assumed, where σVT becomes 130 mV and suppressed to VT can be suppressed to VT becomes 85 and 75 mV, respectively.