A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Authors:
Ahmed A. Eltawil;Michael Engel;Bibiche Geuskens;Amin Khajeh Djahromi;Fadi J. Kurdahi;Peter Marwedel;Smail Niar;Mazen A. R. Saghir
Affiliations:
Center for Embedded Computer Systems, University of California, Irvine, CA, USA;Chair for Embedded Systems, Informatik 12, TU Dortmund, 44221 Dortmund, Germany;Intel Labs, Hillsboro, OR, USA;Intel Labs, Hillsboro, OR, USA;Center for Embedded Computer Systems, University of California, Irvine, CA, USA;Chair for Embedded Systems, Informatik 12, TU Dortmund, 44221 Dortmund, Germany;LAMIH - University of Valenciennes, ISTV2 UVHC, Campus Mont Houy 59313, Valenciennes Cedex 9, France;Texas A&M University at Qatar, Electrical and Computer Engineering Program , P.O. Box 23874, Doha, Qatar
Venue:
Microprocessors & Microsystems
Year:
2013

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Abstract

As systems-on-chip increase in complexity, the underlying technology presents us with significant challenges due to increased power consumption as well as decreased reliability. Today, designers must consider building systems that achieve the requisite functionality and performance using components that may be unreliable. In order to do so, it is crucial to understand the close interplay between the different layers of a system: technology, platform, and application. This will enable the most general tradeoff exploration, reaping the most benefits in power, performance and reliability. This paper surveys various cross layer techniques and approaches for power, performance, and reliability tradeoffs are technology, circuit, architecture and application layers.