Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Reliable and energy-efficient digital signal processing
Proceedings of the 39th annual Design Automation Conference
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies
PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
On The Yield of Compiler-Based eSRAMs
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
System-Level SRAM Yield Enhancement
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
Process variation tolerant low power DCT architecture
Proceedings of the conference on Design, automation and test in Europe
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Low-power filtering via adaptive error-cancellation
IEEE Transactions on Signal Processing
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
Modeling and synthesis of quality-energy optimal approximate adders
Proceedings of the International Conference on Computer-Aided Design
Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Perceptual quality preserving SRAM architecture for color motion pictures
Proceedings of the Conference on Design, Automation and Test in Europe
VaMV: variability-aware memory virtualization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Embedded RAIDs-on-chip for bus-based chip-multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip
Microprocessors & Microsystems
| Hi-index | 0.00 |
Mobile multimedia systems are growing in complexity and scalability and, correspondingly, in their implementation challenges. By design, these systems have built-in error resilience that has been exploited in many different compression and transmission schemes mainly as a quality tradeoff. This paper proposes a paradigm shift in utilizing error resilience in an application-aware method for reducing the power consumption of memories in such systems by aggressively scaling the supply voltage beyond what is currently considered as "safe" operating conditions while maintaining performance. Results on H.264 decoders show that power savings of more than 40% are possible.