Analysis of a Control Mechanism for a Variable Speed Processor
IEEE Transactions on Computers
Microarchitectural dI/dt Control
IEEE Design & Test
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
The First Aysnchronous Microprocessor: The Test Results
The First Aysnchronous Microprocessor: The Test Results
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
Low-power multimedia system design by aggressive voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip
Microprocessors & Microsystems
| Hi-index | 4.10 |
Virtually all engineers use worst case component specifications for new system designs, thereby ensuring that the resulting product will operate under worst-case conditions. However, given that most systems operate under typical operating conditions that rarely approach the demands of worstcase conditions, building such robust systems incurs a significant performance cost. Further, classic worst-case designs do not adapt to variations in either manufacturing or operating conditions.A timing-error-avoidance prototype provides a circuit and system solution to these problems for synchronous digital systems. TEAtime has demonstrated much better performance than classicallydesigned systems and also adapts well to varying temperature and supply-voltage conditions.