Fine-grain voltage tuned cache architecture for yield management under process variations

Authors:
Joonho Kong;Yan Pan;Serkan Ozdemir;Anitha Mohan;Gokhan Memik;Sung Woo Chung
Affiliations:
Division of Computer and Communication Engineering, College of Information and Communication, Korea University, Seoul, South Korea;Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL;Department of Computer Architecture, Universitat Politecnica de Catalunya, Barcelona, Spain;Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL;Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL;Division of Computer and Communication Engineering, College of Information and Communication, Korea University, Seoul, South Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.