Importance sampling for the simulation of highly reliable Markovian systems
Management Science
Fast simulation of rare events in queueing and reliability models
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Selective wordline voltage boosting for caches to manage yield under process variations
Proceedings of the 46th Annual Design Automation Conference
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Statistical SRAM analysis for yield enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
From transistors to MEMS: throughput-aware power gating in CMOS circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A black box method for stability analysis of arbitrary SRAM cell structures
Proceedings of the Conference on Design, Automation and Test in Europe
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Misleading energy and performance claims in sub/near threshold digital systems
Proceedings of the International Conference on Computer-Aided Design
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
ACM Transactions on Embedded Computing Systems (TECS)
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
Proceedings of the great lakes symposium on VLSI
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Proceedings of the Conference on Design, Automation and Test in Europe
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation
Proceedings of the 50th Annual Design Automation Conference
Fine-grain voltage tuned cache architecture for yield management under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for compensating memory errors in JPEG2000
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Voltage scaling is desirable in SRAM to reduce energy consumption. However, commercial SRAM is prone to functional failures when Vdd is scaled. Several SRAM designs scale Vdd to 200--300mV to minimize energy per access, but these designs do not consider SRAM robustness, limiting them to small arrays and sensor type applications. We examine the effects on area and energy for a differential 6T, single-ended 6T with power rail collapsing and an 8T bitcell as Vdd is scaled and the bitcells are sized appropriately to maintain robustness. SRAM robustness is examined using importance sampling to reduce simulation runtime. At high voltages, the differential 6T bitcell is the smallest for the same failure rate, but the 8T bitcell is smaller when Vdd is scaled below 450mV. For Vdd below Vth, bitcells must be sized greatly to retain robustness and large arrays become impractical. The differential 6T and 8T designs have the lowest dynamic energy consumption, and the single-ended 6T design has the lowest leakage. The supply voltage for minimum energy operation depends on cache configuration and can be well above Vth for large caches with low dynamic activity.