Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Power Efficient Data Cache Designs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Yield-driven near-threshold SRAM design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reconfigurable energy efficient near threshold cache architectures
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Hybrid high-performance low-power and ultra-low energy reliable caches
Proceedings of the 8th ACM International Conference on Computing Frontiers
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Proceedings of the Conference on Design, Automation and Test in Europe
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation
Proceedings of the 50th Annual Design Automation Conference
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Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high Vcc, ultra-low Vcc) single-Vcc-domain cache designs have been proposed to tackle the needs of those chips. However, existing data management policies are far from being optimal during high Vcc operation. This paper presents ADAM, a new and extremely simple Adaptive Data Management mechanism, which is tailored to detect hit distribution and changing application conditions dynamically at fine grain with negligible hardware overhead. ADAM is proven to save significant energy (29% on average) in L1 caches with negligible performance degradation (1.7% on average), thus improving the energy-delay product (EDP) noticeably across different cache configurations with respect to all existing data management approaches.