Design Challenges of Technology Scaling
IEEE Micro
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
Proceedings of the great lakes symposium on VLSI
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Proceedings of the Conference on Design, Automation and Test in Europe
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high voltage to provide high performance and at near-/sub-threshold voltage to provide ultra-low energy consumption. This paper studies different non-hybrid and hybrid SRAM L1 cache designs using several SRAM cell types and compare them in terms of delay, dynamic energy, leakage power and area.