Low Vccmin fault-tolerant cache with highly predictable performance
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context
Proceedings of the Conference on Design, Automation and Test in Europe
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Hybrid high-performance low-power and ultra-low energy reliable caches
Proceedings of the 8th ACM International Conference on Computing Frontiers
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
Proceedings of the great lakes symposium on VLSI
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
| Hi-index | 0.00 |
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has approached the limit when direct tunneling causes gate leakage in both on state and off state of MOSFET transistor operation modes. Also, lower operating voltage will lower the stability of SRAM cell resulting in lower value of static noise margin. In this paper, a novel read '0' static noise margin (SNM) free eight transistors (8T) SRAM cell is proposed that reduces gate leakage power in the zero state, taking into consideration the fact that in ordinary program most of the bits stored in caches are zeros for both the data and instruction streams. Compared to conventional six transistors (6T) SRAM cell, new 8T SRAM cell reduces total leakage by 50.2% in the zero state at low temperature, where gate leakage is dominant. High V_T transistors in 8T SRAM cell can be used to further reduce both gate and sub threshold leakage. This new high V_T 8T SRAM cell reduces total leakage by 60% in zero state at highest temperature. The 8T SRAM cell is SNM free in read operation for the case when cell stores logic '0'. Interestingly, new cell improves SNM by 2.2 times as compared to conventional 6T SRAM cell in read operation and standby mode for the case when cell stores logic '1'.